In semiconductor memory devices, data is read from or written to cells in a memory array according to decoded address information and various other control signals. Such memory devices are used for storage of data and/or program code in personal computer systems, embedded processor-based systems, video image processing circuits, communications devices, and the like. Ferroelectric memory, sometimes referred to as FERAM or FRAM memory, provides for storage of data in ferroelectric capacitors, wherein ferroelectric memory cells are commonly provided in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption. In a folded bitline array architecture comprised of 1T1C cells, the individual ferroelectric memory cells typically include a ferroelectric (FE) cell capacitor adapted to store a binary data bit as a polarization state of the capacitor, as well as a MOS access transistor that operates to selectively connect the FE capacitor to one of a pair of complementary bitlines, with the other bitline being connected to a reference voltage. The individual cells are commonly organized as individual bits of a corresponding data word, where the cells of a given word are accessed concurrently by activation of platelines and wordlines by address decoding control circuitry.
Ferroelectric memory devices typically include a number of individually addressable memory cells arranged in an array configuration, wherein the array is typically organized as a matrix of rows and columns. Conventionally, data is stored into a memory array as a row, and read out from the memory array as a row, where the row typically consists of 8, 16, 32, or 64 bits of binary data. During a write operation, row decoder control circuitry provides a plateline pulse signal to first sides of the ferroelectric cells in a data row, the other sides of which are connected to the array bitlines to receive the data. In a read operation, the decoder provides plateline pulses to the first side of each ferroelectric memory cell in a data row, and sense amplifiers (sense amps) are connected to the other side of the cells to sense a row of stored data bits in parallel fashion. Thus, in a single read operation, an entire row of data bits (e.g., 8, 16, 32, or 64 bits) are obtained from the memory cells in the selected row.
The ferroelectric cell capacitors provide data storage in which the ferroelectric dielectric material of the cell capacitors is polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for non-volatile retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within perovskite crystals in the ferroelectric material. This alignment may be selectively achieved by application of an electric field in a first direction that exceeds a coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles, wherein the response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
In a read operation, a reference voltage is typically provided at a first bitline, and the target cell capacitor is connected between a complementary bitline and a plateline pulse signal, thereby causing an electric field to be applied to the cell capacitor. If the applied field is in a direction to switch or reverse the internal dipoles, more charge will be moved than if the dipoles are not reversed. The resulting charge transfer creates a voltage on the data (complementary) bitline. The data bitline voltage, along with the reference voltage on the other bitline, provides a differential voltage on the bitline pair, which is coupled to inputs of a differential sense amp circuit. The sense amp is typically a latch type circuit that measures the charge applied to the cell bitlines and produces either a logic “1” or “0” differential voltage at the sense amp terminals. The reference voltage is typically supplied at an intermediate voltage between the voltage associated with a capacitor storing a binary “0” and that of the capacitor storing a binary “1”.
The polarity of the sensed differential voltage thus represents the data stored in the cell, which is buffered (e.g., latched) by the sense amp and provided to a pair of local IO lines. Reading the data from a ferroelectric memory cell is a destructive operation, in which the previous polarization state of the cell capacitor is not necessarily maintained after reading. Accordingly, the sensed data is restored to the cell following each read operation by application of another pulse to the cell plateline while the sense amp is enabled. In a write operation, an electric field is applied to the cell capacitor by the sense amp or a write buffer, in combination with a plateline activation pulse to polarize the capacitor to the desired data state.
Read/restore and write operations, including the transfer of data between the ferroelectric memory cells, the sense amp circuits, local I/O circuitry, and the local data bitlines, are controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry including address decoders and timing circuits in the device. Such control circuitry generates control signals to trigger a large number of events for controlling wordlines, platelines, precharge devices, sense amps, etc. during memory access operations, wherein the control events are often interdependent and need to follow a certain sequence.
To operate a ferroelectric memory device, whether a stand-alone memory with external address and data I/O connections, or a ferroelectric memory array included within a semiconductor device along with other circuits, various control and timing signals are needed. Conventional timing and control circuits employ a timing or delay chain having a number of series connected fixed delay elements, with a tap at each delay element output that is coupled to a control logic circuit. The control logic circuit generates or derives control signals (e.g., wordline signals, plateline pulses, sense amp enable signals, precharge signals, etc.) according to the delay chain tap outputs.
In manufactured semiconductor devices, electrical circuit component values and overall circuit performance vary based on fabrication processing conditions (e.g., process variation), operating voltages (e.g., voltage variation), and/or operating temperatures (e.g., temperature variations), which are sometimes collectively characterized as process-temperature-voltage (PTV) variations. In typical ferroelectric memory devices, ferroelectric cell capacitors are fabricated in a layer formed above the substrate level in which the cell transistors and control logic transistors are fabricated. The operating parameters of transistors and other electric components in the control circuit delay chain elements typically vary with PTV. Also, the properties of the memory cell access transistors and ferroelectric capacitors vary over PTV.
The PTV variations of the timing and control circuit delay elements, however, typically do not track the PTV variations in the ferroelectric cell capacitors. In particular, CMOS process variations do not necessarily track with the ferroelectric cell capacitor process variations. For example, variations in ferroelectric cell capacitors create a variation in the load of the control circuit plateline drivers, which is typically not correlated to CMOS variations for the plateline driver transistors. The time required to polarize ferroelectric capacitors also varies with processing conditions, temperature, and voltage, where the polarization time is important for read and write operations in high speed (e.g., low access time) memory devices, especially at cold temperatures and low operating voltage, where domain nucleation can be slowed. Minimizing the variability in timing is important in maximizing the reliability of ferroelectric memories. Previously, such variances have been addressed by designing in a significant margin for process variations. However, this is not an option for high performance stand-alone FERAMs and other semiconductor devices that incorporate ferroelectric memory. Accordingly, there is a need for improved delay circuits or control systems for generating control signals in a ferroelectric memory device.